Open JTAG Project

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May-23-2013: New OpenOCD drivers

Thanks to Ryan Corbin for the new OpenOCD driver. You can download the new driver version by clicking here.

Oct-12-2012: Schematic diagram

Thanks to Michael Kuhn from the University of Applied Sciences Darmstadt, Germany, for the updated and well designed OpenJTAG Project schematic diagram. This design uses the FT245RL (no 6MHz quartz required) regards the original FT245BL. You can download it by clicking here.

Jan-09-2012: Board

The OpenJTAG Board has arrived



To project maintenance, we sell the OpenJTAG board. Please click on the above picture or click on the sponsor banner.

Jan-09-2011: Changes

Changes in VHDL code and hardware circuit.

  • VHDL code changes: Fix TAP state machine error
  • Schematic diagram changes: only the output buffer from TXB0104 to TXS0104 pin-to-pin compatible
  • Protocol manual: command patch to add LED's activity

In the download page you can find the USB-Blaster compatibility project.

Please click here to download the latest files.

Nov-28-2010: The project is almost done

Here it is the first version of the OpenJTAG Project driver for OpenOCD.
It is recommended to compile OpenOCD against the FTD2XX drivers since we have seen it is 3 or 4 times faster when used with these drivers. However it works very nice with libftdi drivers too.
It was tested using Eclipse, GDB, OpenOCD, under Linux.

There is still a lot to do (like patching OpenOCD autoconf scripts, test it under Windows, etc.), but we'll get there.

Feel free to try it. Report back any problem you should find!

The Open JTAG Project was tested on a MCBSTM32 board using a Cortex M3 (STM32F103x), GDB and Eclipse under Linux (Ubuntu 10.04

Click here to download the latest files.

Oct-14-2010: Bug fixed in VHDL code.

We found a bug in the TAP state machine. The problem is when the TAP is moving to the Update-IR or Update-DR states. Download the latest Quartus II project.

Please read the License Document before download files.

Oct-2-2010: Bill Of Materials

Click here to download the Bill Of Materials for the Open JTAG project board.

Aug-25-2010: USB Blaster compatibility (Beta stage, but works).

Now you can download the Kolja Waschk project in Quartus II, wired to work with our Open JTAG hardware. We have just tested it using an Altera EPM1270 as target, and seems to work fine.


Due an impedance problems, we think to replace the TXB0104 buffers by the TXS0104, pin-to-pin compatible, but we must wait for the samples. To avoid this problem, you must:

  • Add a 10K pull-down resistor to the TMS pin
  • Add a 10K pull-down resistor to the TDI pin

Aug-15-2010: The project is working (still in Beta stage)

The following photo shows the Windows test program reading the ARM9 Samsung S3C2440A manufacturer code (0x00 0x32 0x40 0x9d). Click to enlarge.

VC6 screenshot

The working project (click to enlarge):

The working proyect

The Open JTAG board and the Altera USB-Blaster board (click to enlarge):

The two JTAG boards


The VHDL code was entirely rewritten, using only 51% of the CPLD capacity.


  • The tap_sm.vhd code was optimized and included inside the serializer.vhd file.
  • The serializer.vhd code was entirely rewritten.
  • Added two control bits in the Set LSB/MSB mode command to control the LED's:
    Bit 5 = 1 blue LED ON, Bit 5 = 0 blue LED OFF
    Bit 6 = 1 red LED ON, Bit 6 = 0 red LED OFF
  • The Return TAP SM state command now returns more information:
    Bit 4 = 1 MSB bit ON, Bit 4 = 0 MSB bit OFF.
    Bit 5 = 1 Target is powered, Bit 5 = 0 Target is unpowered or missing.
  • The Open JTAG board was tested using a maximum TCK clock frequency of 6MHZ. When we tried with 12 MHZ, the Samsung ARM core stopped responding. Samsung claims that the S3C2440A maximum TCK frequency is about 1 MHZ.

To do:

  • Add a new command to shift 32 or 33 bits inside the ARM registers using short transfer time.
  • Add a two new commands to set/get the user I/O pins, good for debug issues.
  • Implement the Adaptive Clock.
  • Fix impedance problem with the TXB0104 buffers.

Download the current project files:

Please read the License Document before download files.

Aug-10-2010: We are working!!

In the following photo you can see the Open JTAG board connected to an ARM9 Samsung S3C2440A.
There is an Altera MAX II development board working as Logical State Analyzer.

We are working

Jul-29-2010: The mounted board.

In the next days the boards will be tested.

Mounted board

Jul-13-2010: The first boards have arrived.

In the next days, the boards will be mounted and tested.


The lastest hardware files could be download. Click here to download.

Jun-12-2010: The Open JTAG project starts.

The Open JTAG project has as objetive to give to the public domain a complete hardware and software JTAG project. Based on a simple hardware board, composed basically by a FT245 USB front end and an Altera EPM570 MAX II CPLD, this board is capable to output TCK signal at 24 MHZ using macro-instructions sent from the computer end.

It is not as others JTAG projects based on the PC parallel port: Open JTAG project uses the USB channel (still not at full speed) to communicate with the internal CPLD, sending macro-instruction as fastest as possible. The complete project (Beta version) is available here or at


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