Open JTAG Project

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openjtag-pub


Note: The full project could be emulated in the Altera MAX II Development Kit. Click here to viiew Altera page

The hardware project is mainly composed of:

  • 1 two-layer PCB
  • 1 FTDIChip FT245BL USB to Parallel converter
  • 1 Altera EPM570T100 TQFP100 CPLD
  • 1 generic 93C46 serial EEPROM
  • 1 IQD SPXO018043 48 MHZ oscillator
  • 1 generic HC49 6MHZ quartz
  • 1 ST Microelectronics LK112M33TR 3.3V LDO regulator
  • 2 Texas TXS0104 bidirectional level converter

The circuitry is simple and easy to understand. The FT245 is the USB front end, converting USB serial data to parallel bus to interface with the EPM570 CPLD. The CPLD latch the parallel data and execute macro-instruction commands, driving the main five JTAG signals: TCK, TMS, TDI, TDO and TRST.

Inside the CPLD there is a synthesized clock divisor to work with slow target devices. The higher TCK frequency is 24 MHZ (main clock / 2) and the lower frequency is 187.5 KHZ.

The board have 8 input/output pins (J4 connector) to be used as general purpose I/O.

The PCB size is 57.2mm x 43.3mm (2.26" x 1.7") and fits inside the Altera USB Blaster plastic box, and it is pin-to-pin compatible. The same JTAG flat cable can be used.

There is another projetc from Kolja Waschk (http://www.ixo.de) to create an Altera USB Blaster compatible JTAG. The Kolja project could be implemented in our hardware. We have tested the project using Quartus II 9.0 and seems to work fine. Please click here to download the Quartus II Kolja project, ready to be used in our hardware.

Board:

 

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