Open JTAG Project

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Welcome to Open JTAG Project

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Mar-04-2014: New project start

Dear friends, the OpenJTAG team launch a new and exciting project: OpenJTAG2 board.

As the Altera CPLD devices becomes more expensive, this time we try with a Lattice MachX02 device having 1200 LUT's (twice as Altera) with half price.

Lattice MachX02 features:

Non volatile memory
1200 LUT's
74 Kbits EBR RAM
7 EBR RAM Blocks (9 Kbits/block)
10 Kbits Dist. SRAM
80 Kbits User Flash Memory
1 PLL
1 embedded SPI
1 embedded I2C
100 pin TQFP package

The new OpenJTAG2 board performs:

2 layer PCB
1 Lattice MachX02-1200 FPGA
1 High Speed (10 ns) 128KB static RAM
1 MB external SPI flash memory

1 20 pin standard ARM IDC connector for ETM
1 20 pin standard ARM IDC connector for JTAG
1 FT240X for the USB-to-Parallel bridge
2 user LED's
1 user KEY
1 48 MHz oscillator
1 2x8 connector with GND, Power and 12 free FPGA I/O pin
1 6 pin connector for FPGA programming
10 dedicated FPGA pins buffered with bidirectional level translators and tri-state capabilities
800 mA power supply (usable only 500mA from USB connector)
Target power detector

NOTE: The FPGA is powered at 3.3V only.


The prototype board is no ready yet, but you can get the schematics diagram by click the link below. Note that the schematics diagram is subject to changes. All changes will be published in our site.

Download the schematic diagram here

The first PCB prototype is already routed. The next pictures are a 3D renderization of the OpenJTAG2 BOARD

OpenJTAG_V2

Have fun!
The OpenJTAG Team


 

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